The present invention generally relates to semiconductor devices, and more particularly to an SOI (silicon-on-insulator) device that is suitable for integration on a common substrate with improved breakdown voltage.
The use of so-called SOI devices is expanding particularly for devices that are required to have a high breakdown voltage. For example, the SOI devices are used commonly for display drivers. Further, a SOI devices are suited for use in the radiation environment. Even in the applications of SOI devices, there is a persisting demand to increase the operational speed of the device.
Generally, the SOI devices are formed on a layered semiconductor body that includes a silicon substrate, a silicon oxide insulation formed on the substrate and an active layer that is formed on the silicon oxide insulation layer. Such a structure can be formed by bonding a single crystal silicon layer, acting as the active layer on the oxide insulation that in turn is formed on the silicon substrate, at a high temperature. Particularly, when the thickness of the silicon oxide insulation layer is reduced, the device shows various advantageous features such as the elimination of so-called short channel effect, the improvement of output current, and the like. Thus, efforts are made to reduce the thickness of the silicon oxide insulation layer.
In such SOI devices, however, there is a tendency that a punch-through current flows from the source to the drain, particularly when the thickness of the silicon oxide insulation layer is thin and a large drain voltage is applied. This is believed to be caused by the potential of the silicon substrate that is located under the silicon oxide insulation layer. Because of the reduced thickness of the silicon oxide insulation layer, the potential of the silicon substrate acts as the gate voltage and the current flows unwantedly from the source to the drain along the bottom surface of the active layer. In order to eliminate this so-called backchannel effect, application of a bias voltage to the substrate is proposed to eliminate the conduction along the bottom surface of the silicon active layer.
Referring to FIG. 1 showing a typical SOI device 10, the device 10 comprises an n-channel MOS transistor formed on a silicon active layer 11 that in turn is formed on a silicon oxide insulation 12, and the silicon oxide insulation 12 is formed on a silicon substrate 13. Further, the silicon substrate 13 is applied with a bias voltage V.sub.bias such that no punch-through current flows from a source 11a to the drain 11b along the channel formed along the insulation layer 12.
In the n-channel MOS transistor, a positive voltage is used as the bias voltage V.sub.bias. This conventional construction, however, has an obvious problem of inapplicability to the CMOS devices wherein n-channel MOS transistors and p-channel MOS transistors are formed on a common substrate. In order to achieve this, one requires a complex structure and hence a complex process.
Further, such a conventional SOI device has suffered from a problem of leakage current flowing along the silicon oxide layer 12. It should be noted that the silicon oxide layer 12 is exposed to the environment for a long time after it is formed on the surface of the silicon substrate 13. Thereby, there is a tendency of the silicon oxide layer collect impurities on the surface thereof, and such impurities degrade the quality of the interface between the silicon oxide layer 12 and the silicon layer 11 formed thereon.